Modern integrated circuits (ICs), can include millions of transistors fabricated in and on a semiconductor substrate. In making a mask to fabricate such a complex device, a circuit design layout will pass through a variety of filters, checks, and modifications before being taped out to a mask. Ideally, the process results in a mask that is used to lithographically fabricate a final circuit design layout on a semiconductor substrate without printing defects and without defects in the fabricated final circuit layout.
The circuit design layout may contain standard cells and standard device designs as well as new cell and device designs, and generally complies with rigid design rules that include minimum feature size, minimum spacing between device elements, and the like. To improve functional and yield characteristics of the circuit design layout, the circuit design layout generally passes through multiple simulations, many of which are time consuming. Short cuts are available to reduce simulation time, and hence cost, without sacrificing accuracy of the final circuit layout. One method for providing approximate but fast evaluation of sensitivity of the circuit design layout to lithographic effects that can affect variability and yield is pattern matching. Pattern matching is particularly known for use to determine lithographic or printability problems. Printability problems are problems in which a circuit design layout on a mask, for example a particular array of lines and spaces, cannot be accurately reproduced in or on a semiconductor substrate by etching through the circuit design layout on the mask. In conventional pattern matching techniques, element patterns in the circuit design layout that are known to cause printability problems are first identified by comparing element patterns in the circuit design layout at sensitive locations to a library of problematic element patterns. The library of problematic element patterns is generally developed in collaboration between a design house and their foundry partner and is further recorded to enable the problematic element patterns to be avoided in implementing future designs or design revisions. In practice, an evolving layout pattern can be subjected to pattern matching software to identify patterns in the layout design that are similar to the library patterns.
Upon identifying element patterns in the circuit design layout that are similar to problematic element patterns in the library, existing techniques involve changing the problematic element patterns through a global rule change that is applied based upon the identified defect in the problematic element pattern. In particular, the global rule change involves modifying a particular design parameter that is responsible for the problems associated with particular problematic element features, with the modification applied across the entire circuit design layout. However, the global approach to modifying the entire circuit design layout may result in modifications to the circuit design layout that may be unnecessary or that may cause unintended problems at various locations within the circuit design layout.
Accordingly, it is desirable to provide methods for modifying the physical design of an electrical circuit used in the manufacture of a semiconductor device that enables a local approach to alleviating problematic element patterns and that avoids unintended modifications to the circuit design layout that may be unnecessary or that may cause unintended problems after modification of the problematic element patterns. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.